GOA (Gate Driver on Array) skill is to integrate the TFT (Thin Film Transistor) of a gate driving circuit on the array substrate and to eliminate the integrated circuit part of the gate driving circuit located outside the array substrate. Accordingly, two aspects of material cost and process is considered to reduce the manufacture cost of the productions. GOA skill is a common gate driving circuit skill used in a present TFT-LCD (Thin Film Transistor-Liquid Crystal Display). The manufacture process is simple and provides great application possibilities. The functions of the GOA circuit mainly comprises: the present gate line outputs a high level signal with charging the capacitor of the shift register unit by using the high level signal outputted from the previous gate line, and then reset is achieved by using the high level signal outputted from the next gate line.
Please refer to FIG. 1, which is a single level structural diagram of a GOA circuit commonly employed in panel display according to prior art. It comprises: a plurality of GOA units which are cascade connected, and a nth gate driver on array unit controls charge to a nth horizontal scanning line G(n) in a display area, and the nth gate driver on array unit comprises pull-up controlling part 1′, a pull-up part 2′, a transmission part 3′, a first pull-down part 4′ (Key pull-down part), a bootstrap capacitor part 5′ and a pull-down holding part 6′ (Pull-down holding part). The pull-up part 2′, the first pull-down part 4′, the bootstrap capacitor part 5′ and the pull-down holding part 6′ are respectively coupled to a Nth gate signal point Q(n) and the Nth horizontal scanning line G(n), and the pull-up controlling part 1′ and the transmission part 3′ are respectively coupled to the Nth gate signal point Q(n), and the pull-down holding part 6′ is inputted with a DC low voltage VSS.
The pull-up controlling part 1′ comprises a first thin film transistor T1′, and a gate of the first thin film transistor T1′ is inputted with a transmission signal ST(N−1) from the N−1th GOA unit, and a drain is electrically coupled to the N−1th horizontal scanning line G(N−1), and a source is electrically coupled to the Nth gate signal point Q(N); the pull-up part 2′ comprises a second thin film transistor T2′, and a gate of the second thin film transistor T2′ is electrically coupled to the Nth gate signal point Q(N), and a drain is inputted with a first high frequency clock CK or a second high frequency clock XCK, and a source is electrically coupled to the Nth horizontal scan line G(N); the transmission part 3′ comprises a third thin film transistor T3′, and a gate is electrically coupled to the Nth gate signal point Q(N), and a drain is inputted with a first high frequency clock CK or a second high frequency clock XCK, and a source outputs a Nth transmission signal ST(N); the first pull-down part 4′ comprises a fourth thin film transistor T4′, and a gate of the fourth thin film transistor T4′ is electrically coupled to the N+1th horizontal scan line G(N+1), and a drain is electrically coupled to the Nth horizontal scan line G(N), and a source is inputted with the DC low voltage VSS; a fifth thin film transistor T5′, and a gate of the fifth thin film transistor T5′ is electrically coupled to a N+1th horizontal scan line G(N+1), a drain is electrically coupled to the Nth gate signal point Q(N), and a source is inputted with the DC low voltage VSS; the bootstrap capacitor part 5′ comprises a bootstrap capacitor Cb′; the pull-down holding part 6′ comprises a sixth thin film transistor T6′, and a gate of the sixth thin film transistor T6′ is electrically coupled to a first circuit point P(N)′, and a drain is electrically coupled to the Nth horizontal scan line G(N), and a source is inputted with the DC low voltage VSS; a seventh thin film transistor T7′, and a gate of the seventh thin film transistor T7′ is electrically coupled to a first circuit point P(N)′, and a drain is electrically coupled to Nth gate signal point Q(N), and a source is inputted with the DC low voltage VSS; an eighth thin film transistor T8′, and a gate of the eighth thin film transistor T8′ is electrically coupled to a second circuit point K(N)′, and a drain is electrically coupled to the Nth horizontal scan line G(N), and a source is inputted with the DC low voltage VSS; a ninth thin film transistor T9′, and a gate of the ninth thin film transistor T9′ is electrically coupled to the second circuit point K(N)′, and a drain is electrically coupled to the Nth gate signal point Q(N), and a source is inputted with the DC low voltage VSS; a tenth thin film transistor T10′, and a gate of the tenth thin film transistor T10′ is inputted with a first low frequency clock LC1, and a drain is inputted with a first low frequency clock LC1, and a source is electrically coupled to the first circuit point P(N)′; an eleventh thin film transistor T11′, and a gate of the eleventh thin film transistor T11′ is inputted with a second low frequency clock LC2, and a drain is inputted with the first low frequency clock LC1, and a source is electrically coupled to the first circuit point P(N)′; a twelfth thin film transistor T12′, and a gate of the twelfth thin film transistor T12′ is inputted with the second low frequency clock LC2, and a drain is inputted with the second low frequency clock LC2, and a source is electrically coupled to the second circuit point K(N)′; a thirteenth thin film transistor T13′, and a gate of the thirteenth thin film transistor T13′ is inputted with the first low frequency clock LC1, and a drain is inputted with the second low frequency clock LC2, and a source is electrically coupled to the second circuit point K(N)′; a fourteenth thin film transistor T14′, and a gate of the fourteenth thin film transistor T14′ is electrically coupled to the Nth gate signal point Q(N), and a drain is electrically coupled to the first circuit point P(N)′, a source is inputted with the DC low voltage VSS; a fifteenth thin film transistor T15′, and a gate of the fifteenth thin film transistor T15′ is electrically coupled to the Nth gate signal point Q(N), and a drain is electrically coupled to the second circuit point K(N)′, and a source is inputted with the DC low voltage VSS; wherein the sixth thin film transistor T6′ and the eighth thin film transistor T8′are in charge of keeping the low voltage level at the Nth horizontal scan line G(N) in the non functioning period. The seventh thin film transistor T7′ and the ninth thin film transistor T9′ are in charge of keeping the low voltage level at the Nth gate signal point Q(N) in the non functioning period.
From the viewpoint of overall circuit structure, the pull-down holding part 6′ is in a state of having a longer working period. In other word, the first circuit point P(N)′ and the second circuit point K(N)′ are in a positive high voltage state for a long period of time. Under the most serious voltage stresses are the thin film transistors T6′, T7′, T8′, T9′. Along with the increase of the working period of the gate driving circuit, the threshold voltages Vth of the thin film transistors T6′, T7′, T8′, T9′ are gradually increased and the activation currents are gradually decreased. Thus, the Nth horizontal scan line G(N) and the Nth gate signal point Q(N) cannot be well kept in a steady low voltage level state. This is a significant factor of influencing the reliability of the gate driving circuit.
For an amorphous silicon TFT gate driving circuit, the pull-down holding part is essential. In general, the design can be one pull-down holding part, or two alternately functioning pull-down holding parts. The main objective of the design of the two alternately functioning pull-down holding parts is to the voltage stress applying to the thin film transistors T6′, T7′, T8′, T9′ controlled by the first circuit point P(N)′ and the second circuit point K(N)′ in the pull-down holding part. However, it is found with actual measurement that the four thin film transistors T6′, T7′, T8′, T9′ still suffer the most serious voltage stress in the entire gate driving circuit even the design of two alternately functioning pull-down holding parts is applied. Thus, the threshold voltages (Vth) of these thin film transistors drift most.
Please refer to FIG. 2a, which is a relationship diagram of the overall current logarithm and the voltage curve of the thin film transistor before and after the threshold voltage drift. The full line is the relationship curve of the current logarithm and the voltage that the threshold voltage drift does not occur. The dotted line is the relationship curve of the current logarithm and the voltage that the threshold voltage drift occurs. As shown in FIG. 2a, the current logarithm Log(Ids) that no threshold voltage drift occurs is larger than the current logarithm that the threshold voltage drift occurs under the circumstance of the same gate-source voltage Vgs. Please refer to FIG. 2b, which is a relationship diagram of the overall current and the voltage curve of the thin film transistor before and after the threshold voltage drift. As shown in FIG. 2b, the gate voltage Vg1 that no threshold voltage drift occurs is larger than the gate voltage Vg2 that the threshold voltage drift occurs under the circumstance of the same gate-source current Ids. Thus, after the threshold voltage drift occurs, a larger gate voltage is necessary once reaching the same level source current Ids is requested.
As shown in FIG. 2a and FIG. 2b, threshold voltage Vth drifts toward the positive and the activation current Ion of the thin film transistor is gradually decreased. The activation current Ion of the thin film transistor will gradually decrease along with the increase of the threshold voltage Vth. Thus, to the circuit, the voltage level of the Nth horizontal scan line G(N) and the Nth gate signal point Q(N) cannot be well kept in a steady state. Consequently, an abnormal image display of the liquid crystal display will happen.
As aforementioned, the most possible failed elements are the thin film transistors T6′, T7′, T8′, T9′ of the pull-down holding part. Therefore, this issue has to be solved for promoting the reliabilities of the gate driving circuit and the liquid crystal display panel. In a common and normal design, the dimensions of these four thin film transistors T6′, T7′, T8′, T9′ are increased. However, the deactivation leak current of the working thin film transistors will increase when the dimensions of the thin film transistors are increased and the issue cannot be substantially solved.